Wednesday, March 12, 2014

ABOUT COPROCESSOR INTEL XEON PHI

ABOUT coprocessor INTEL XEON PHI
ABOUT COPROCESSOR INTEL XEON PHI

Intel has long and firmly holds a very large share of the video card market. This situation persists due to the wide spread of built-in graphics cards. For example, the accelerator Intel HD Graphics 3000 is the second largest (3.8%) in the list of Steam for distribution among the users of the service, despite the fact that it is not a full game graphics card.


However, the profit from the sale of such embedded adapters, in fact, missing, and such a large and ambitious company like Intel, could not always be kept away from the fast-growing market of discrete graphics cards. And back in 2006 there were the first rumors that Intel is preparing a discrete graphics card. In a short time the rumors turned into details, narrated by Paul Otellini at the 2007 forum IDF, and extend the set of reliable information. It was learned that future products, code-named Larrabee, will be based on the x86 architecture that will be based on old, but modernized architecture processor Pentium P54C.


Each year, information from Intel appeared more and more, however, no graphics Larrabee has not been released. Intel has not been able to obtain from the proper performance of their offspring for a worthy competition to growing monster graphics from ATI and NVIDIA. Instead, it changed the name and direction and turned first into a project called Intel Knights Ferry, and then changing the manufacturing process, in the 22-nanometer processor Knights Corner with more than 50 cores aimed at the segment of parallel computing.


Common name of projects to develop this architecture has been called Many Integrated Core (MIC).

Today the final version of the long-term transformation is a product called the Intel Xeon Phi, samples of which are based on the stepping B0, Intel began sending some partners last week.

Xeon Phi chips are created on 22-nanometer process technology. The coprocessor is an expansion board for the bus PCI Express. Presumably five modifications will be available in the coprocessor chips and will include 57, 60, or 61 core. Cache size of the first level will range from 1.8 to 1.9 MB cache second level - from 28 to 30.5 MB. The novelty will have GDDR5 memory capacity of 3, 6, or 8 GB.


The minimum frequency of the kernel version with 57 cores will be equal to 600 MHz, the maximum value will reach 1.1 GHz Memory - 3 or 6 GB. Modifications 60 and core 61 will operate at a frequency from 630 MHz to 1.05 GHz and 1.09 respectively, and have a storage capacity of 8 GB. All versions will support analog technology Turbo Boost, but the details of its work products Xeon Phi not. The memory frequency will be between 5-5.5 GHz, and its capacity will reach 300 GB / sec. Power is at 245 watts for 57 version nuclei (3 GB) and the kernel version 61 (GB 6), whereas for the 57-core modification and 6 GB versions 60 and 61 and core 8 GB TDP of 300 watts.


Almost all versions of Xeon Phi will be equipped with passive cooling, with the exception of 57-core versions with 6 GB of memory, which will receive the active cooling system.